1. Field of the Invention
Generally, the present disclosure relates to integrated circuits, and, more particularly, to the generation and control of capture clocks used during scan and built-in self-testing of integrated circuits.
2. Description of the Related Art
Design-for-Testability (DFT) is a technique that enhances a microcircuit's testability by incorporating certain features into the microcircuit's design to facilitate testing of the manufactured product. The goal of such a design is to make difficult-to-test sequential circuits easier to test by replacing traditional sequential elements, such as flip flops (hereinafter called flops) with scannable sequential elements, called scan cells, and then connecting the scan cells together to form scan chains. A scan cell is a normal latch or flip-flop with an additional input, called the scan input, and an additional output, called the scan output. The scan output of one scan cell connects to the scan input of the next scan cell to form the scan chain. The scan cells connect to the core logic and become part of the core design. With the added inputs and outputs that form the scan chains, you can shift data serially into and out of the core logic to inject test patterns into, or receive test results from, a manufactured microcircuit design.
Each scan cell of the scan chain serves as both a control and an observation point for Automatic Test Pattern Generation (ATPG) testing and fault simulation. ATPG tools automatically generate test patterns for use in the scan chains. Automatic Test Equipment (ATE) shifts these test patterns into the scan chains and supplies, or causes to be supplied, one or more clock pulses to the core logic. The responses to the test patterns are captured within the scan cells and the results are shifted out of the scan chain. ATE then compares the results with expected results to determine if a fault is present.
Many test patterns are typically generated and used during scan testing. Different test patterns provide different test coverage. A pattern having high test coverage typically tests many different parts of the design while a pattern having low test coverage tests only smaller portions. To meet a test budget, it is desirable to move test patterns with high test coverage to the beginning of a pattern set and test patterns with low test coverage to the end of the pattern set or drop them altogether.
Because each test pattern usually requires a different number of at-speed clock pulses to be applied to the scan chain, test patterns are typically ordered by the number of at-speed clock pulses each requires. Ordering test patterns by the required number of clock pulses reduces the number of times the clock circuitry must be adjusted during test. A typical scan test cycle includes shifting a scan test pattern into the scan chain, pulsing a system clock one or more times to capture test results within the scan chain, and shifting the results out. A capture cycle is that portion of the scan test that captures the test results.
Boundary-Scan Testing, also known as the Joint Test Action Group (JTAG) standard, or IEEE 1149.1, is another test architecture known in the art. Among other things, it provides a means for testing integrated circuits within the core logic by, for example, initiating logic built-in self-test (LBIST), without using physical test probes. JTAG architecture adds boundary-scan cells to each pin on a microcircuit device and to core logic so that test and control data can be injected into the logic, tests can be initiated, and the results shifted out, even when the microcircuit is encased in a package. JTAG registers and control circuitry interact with other circuitry within a microcircuit device to initiate and control internal testing.